LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY TestRegistre IS END TestRegistre ; ARCHITECTURE Simulation OF TestRegistre IS COMPONENT Registre GENERIC (Treg: TIME ; NbBits : INTEGER); PORT ( load : IN Std_Logic ; D : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; Q : OUT Std_Logic_Vector(NbBits-1 DOWNTO 0) ); END COMPONENT ; SIGNAL s_load : Std_Logic := '0' ; SIGNAL s_D : Std_Logic_Vector(7 DOWNTO 0) ; SIGNAL s_Q : Std_Logic_Vector(7 DOWNTO 0) ; BEGIN Reg1 : Registre GENERIC MAP (8 ns, 8 ) PORT MAP (s_load, s_D, s_Q ); Simule : PROCESS BEGIN s_D <= (OTHERS => '0') ; s_load <= '0'; WAIT FOR 5 ns; s_D <= (OTHERS => '0') ; s_load <= '1'; WAIT FOR 5 ns; s_D <= (OTHERS => '0') ; s_load <= '0'; WAIT FOR 5 ns; s_D <= "01010101" ; s_load <= '0'; WAIT FOR 5 ns; s_D <= "01010101" ; s_load <= '1'; WAIT FOR 5 ns; s_D <= "01010101" ; s_load <= '1'; WAIT FOR 5 ns; s_D <= "11001100" ; s_load <= '0'; WAIT FOR 5 ns; s_D <= "11001100" ; s_load <= '1'; WAIT FOR 5 ns; s_D <= "11001100" ; s_load <= '0'; WAIT FOR 5 ns; WAIT ; END PROCESS Simule; END Simulation ;