LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY Registre IS GENERIC (Treg: TIME ; NbBits : INTEGER); PORT ( load : IN Std_Logic ; D : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; Q : OUT Std_Logic_Vector(NbBits-1 DOWNTO 0) ); END Registre ; ARCHITECTURE comportementale OF Registre IS BEGIN ProcessRegistre : PROCESS (load, D) BEGIN IF load = '1' THEN Q <= D AFTER Treg ; END IF ; END PROCESS ProcessRegistre ; END comportementale ;