LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_SIGNED.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; USE work.UALPack.all; ENTITY TestUAL IS END TestUAL ; ARCHITECTURE test OF TestUAL IS COMPONENT UAL GENERIC ( NbBits : INTEGER := 16 ) ; PORT ( Entree1 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; Entree2 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; cmdUAL : IN Std_Logic_Vector(Log2NbFonctions-1 DOWNTO 0) ; CptRendu : OUT Std_Logic_Vector(NbCptRendu-1 DOWNTO 0) ; Sortie : OUT Std_Logic_Vector(NbBits-1 DOWNTO 0) ); END COMPONENT ; SIGNAL sEntree1 : Std_Logic_Vector(7 DOWNTO 0) ; SIGNAL sEntree2 : Std_Logic_Vector(7 DOWNTO 0) ; SIGNAL scmdUAL : Std_Logic_Vector(Log2NbFonctions-1 DOWNTO 0) ; SIGNAL sCptRendu : Std_Logic_Vector(NbCptRendu-1 DOWNTO 0) := (OTHERS => '0') ; SIGNAL sSortie : Std_Logic_Vector(7 DOWNTO 0) := (OTHERS => '0') ; TYPE TableauEntrees IS RECORD In1 : Std_Logic_Vector(7 DOWNTO 0); In2 : Std_Logic_Vector(7 DOWNTO 0); Cmd : Std_Logic_Vector(Log2NbFonctions-1 DOWNTO 0); END RECORD; TYPE TableauVecteurs IS ARRAY (INTEGER RANGE <>) OF TableauEntrees; CONSTANT TempsCycle : TIME := 100 ns; CONSTANT Vecteurs : TableauVecteurs := ( ( CONV_STD_LOGIC_VECTOR(12, 8), CONV_STD_LOGIC_VECTOR(35, 8), F_ADD ), ( CONV_STD_LOGIC_VECTOR(4, 8), CONV_STD_LOGIC_VECTOR(123, 8), F_AND ) ); BEGIN UAL1 : UAL GENERIC MAP (8) PORT MAP (sEntree1, sEntree2, scmdUAL, sCptRendu, sSortie); ProcessSimulation : PROCESS BEGIN WAIT FOR TempsCycle ; FOR I IN Vecteurs'RANGE(1) LOOP sEntree1 <= Vecteurs(i).In1; sEntree2 <= Vecteurs(i).In2; scmdUAL <= Vecteurs(i).Cmd; WAIT FOR TempsCycle; END LOOP; WAIT ; END PROCESS ProcessSimulation; END test ;