LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY PorteXor IS GENERIC ( TXor : TIME ; NbBits : INTEGER ); PORT ( entree1 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; entree2 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; sortie : OUT Std_Logic_Vector(NbBits-1 DOWNTO 0) ) ; END PorteXor ; ARCHITECTURE comportementale OF PorteXor IS BEGIN sortie <= entree1 XOR entree2 AFTER TXor; END comportementale ;