LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE work.PackProj.All; ENTITY Validation IS GENERIC ( NbBits : INTEGER; TValid : TIME ); PORT ( Entrees : IN Std_Logic_Vector(NbBits -1 DOWNTO 0) ; Valide : IN Std_Logic ; Sorties : OUT Std_Logic_Vector(NbBits -1 DOWNTO 0) ); END Validation; ARCHITECTURE Flot OF Validation IS BEGIN Sorties <= Entrees AFTER TValid WHEN Valide = '0' else (OTHERS => '0') AFTER TValid ; END Flot;