LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY PorteNor IS GENERIC (TNor : TIME ; NbBits : INTEGER ); PORT (entree1 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; entree2 : IN Std_Logic_Vector(NbBits-1 DOWNTO 0) ; sortie : OUT Std_Logic_Vector(NbBits-1 DOWNTO 0) ) ; END PorteNor ; ARCHITECTURE comportementale OF PorteNor IS BEGIN sortie <= entree1 NOR entree2 AFTER TNor; END comportementale ;