LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;

ENTITY Demultiplexeur IS
	GENERIC (
		TDemux : TIME ;
		NbBits : INTEGER   
	);
	PORT    (
		entree  : IN  Std_Logic_Vector(NbBits-1 DOWNTO 0) ;
		cmd 	  : IN Std_Logic ;
		sortie1  : OUT  Std_Logic_Vector(NbBits-1 DOWNTO 0)       ;
		sortie2  : OUT  Std_Logic_Vector(NbBits-1 DOWNTO 0) 
	) ;
END Demultiplexeur ;

ARCHITECTURE comportementale OF Demultiplexeur IS 
	SIGNAL s_inter1 : Std_Logic_Vector(NbBits-1 DOWNTO 0);
	SIGNAL s_inter2 : Std_Logic_Vector(NbBits-1 DOWNTO 0);
BEGIN
	s_inter1 <= 	entree WHEN cmd = '0' ELSE 
			(OTHERS => 'Z') ;
			
	s_inter2 <= 	entree WHEN cmd = '1' ELSE 
			(OTHERS => 'Z') ;
	
	sortie1 <= s_inter1 AFTER TDemux;
	sortie2 <= s_inter2 AFTER TDemux;
END comportementale ;